The invention relates to a circuit array with a microprocessor having a first pulse generator for operating a liquid-crystal display (LCD) using the time-division multiplexing method, said array having at least one backplane and several segments, each backplane being allocated a backplane pulse sequence, a segment pulse sequence being specified for every possible combination of picture points on a segment and all pulse sequences periodically having clock-timed intervals of corresponding length and number, with driving stages for the segments generating the segment pulse sequences depending on the data signals supplied to the circuit array, and with a shift register array storing the supplied data signals, this array having a number of stages corresponding to the number of segments.
A circuit array of this type is known from German patent DE-PS 29 39 553. Here, a liquid-crystal display LCD is controlled with backplane pulse sequences R1, R2, R3 and segment pulse sequences SA, . . . , SH, for which purpose pulse patterns corresponding to the pulse sequences are emitted from a read-only memory ROM, which is programmable if necessary. The read-only memory ROM is controlled by a circuit INFO, for example a data-processing unit, with which the information to be displayed by the liquid-crystal display LCD can be emitted depending on a transfer signal TO of the read-only memory ROM. The pulse patterns corresponding to the pulse sequences are compiled in the read-only memory ROM depending on the information to be displayed and transmitted by the circuit INFO, and by means of pulse signals of differing pulse length. The pulse pattern for the backplane pulses is emitted in parallel to a memory STR, "parallel", connected behind the read-only memory ROM and the pulse pattern for the segment pulses emitted in series to a shift register array, "serial", connected behind the read-only memory ROM. The two memories STR and STS have a number of memory cells for parallel supply of the pulses that corresponds to the number of backplanes or segments of all display points. The pulse signals of differing pulse length are supplied by a frequency divider FT which additionally supplies a transfer pulse TC to the memory STS connected behind the shift register array SR and to the memory STR, which in their turn control the liquid-crystal display LCD. The read-only memory ROM and the frequency divider FT are controlled with the pulses of a time-clock generator CL that in addition generates the shift pulse for the shift register array SR. The shift register array SR has a number of stages corresponding to the total number of segments present in the liquid-crystal display. The memory STS controlling the liquid-crystal display LCD operates not only as a memory circuit, but also as a voltage adjusting circuit, where the voltage of the signals to be emitted by the memory adapts to the requirements set by the liquid-crystal display LCD.
The generation of the pulse patterns causing the pulse sequences for the backplanes and the segments in a single control circuit common to all the display points does however have the drawback that only a certain configuration of a liquid-crystal display is feasible, for example a four-digit liquid-crystal display operated by a three-step multiplexing method, with each display point having three backplanes and three segments (see embodiment as per FIG. 4 of the above patent). It was therefore not possible to operate a liquid-crystal display with less than three backplanes and three segments with this circuit array, since decoding of the data signals transmitted by the circuit INFO--for example a data-processing device--to the read-only memory ROM as well as the composition of the pulse patterns corresponding to the backplane or segment pulse sequences in the read-only memory ROM is fixed by the hardware. Since the data-processing system controlling the read-only memory ROM, for example a microprocessor, must emit the information to be displayed by the liquid-crystal display in a form compatible for the read-only memory ROM, a different configuration of a liquid-crystal display could only be designed by changing the internal structure of the microprocessor and if necessary also the number of stages of the shift register and of the memories STR and STS. This would however represent an unacceptable expense, as a different microprocessor would have to be developed for each different configuration of liquid-crystal display. The flexibility of a circuit array of this type for controlling a liquid-crystal display is therefore considerably restricted by the connection of a read-only memory ROM, which performs at the same time the generation of the pulse patterns corresponding to the backplane or segment pulse sequences.
For example, the microcomputer LCD-III developed by Hitachi (data sheet "Hitachi microcomputer Databook 4-bit single-chip", September 1984, pages 273 to 298) for direct control of a liquid-crystal display offers the possibility of software selection of the multiplexing rate, with the pulse patterns corresponding to the backplane or segment pulse sequences being held in readiness in the main memory of the processor, in order to be read into a read-write memory RAM when the liquid-crystal display is operating in multiplex mode; from there they are shifted into a shift register and then read out in parallel into a memory whose number of memory locations corresponds to the number of segments. Finally, this data is supplied directly to the driving stages controlling the segments. A drawback here is that the control of the liquid-crystal display is shut down, i.e. the display goes out, when the microprocessor is stopped for power economy reasons. Also, the microprocessor is subjected to an unnecessarily high load, since the shift register has to be reloaded with data for every clock pulse.